By M.C. Bhuvaneswari
This booklet describes how evolutionary algorithms (EA), together with genetic algorithms (GA) and particle swarm optimization (PSO) can be used for fixing multi-objective optimization difficulties within the sector of embedded and VLSI process layout. Many complicated engineering optimization difficulties should be modelled as multi-objective formulations. This booklet offers an creation to multi-objective optimization utilizing meta-heuristic algorithms, GA and PSO and the way they are often utilized to difficulties like hardware/software partitioning in embedded structures, circuit partitioning in VLSI, layout of operational amplifiers in analog VLSI, layout area exploration in high-level synthesis, hold up fault checking out in VLSI trying out and scheduling in heterogeneous allotted structures. it really is proven how, in each one case, some of the facets of the EA, specifically its illustration and operators like crossover, mutation, and so forth, might be individually formulated to resolve those difficulties. This booklet is meant for layout engineers and researchers within the box of VLSI and embedded procedure layout. The e-book introduces the multi-objective GA and PSO in an easy and simply comprehensible manner that would entice introductory readers.
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Extra resources for Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems
Mi and Nj are the total area of the nodes in partition 1 and partition 2, respectively. C. Bhuvaneswari and M. Jagadeeswari NETS CUT B1 B2 B4 B8 B3 B6 B5 PARTITION 1 B7 PARTITION 2 B1 0 B2 0 B3 1 B4 0 5B 1 B6 1 B7 1 B8 0 ENCODING SCHEME Fig. 2 Chromosome representation for circuit bipartitioning problem (C) so that the number of nets cut is optimized and also to balance the two partitions by placing equal number of components in each partition. This is evaluated by calculating the area imbalance.
In: Proceedings of the 14th IEEE ASIC/SOC conference, 12–15 Sept 2011, Arlington, pp 242–247 Madsen J, Grode J, Knudsen P (1997) Hardware/software partitioning using the LYCOS system. Hardware/software codesign: principles and practices, Springer, US Niemann R, Marwedel P (1997) An algorithm for hardware/software partitioning using mixed linear programming. Des Autom Embed Syst 2(2):165–193 Schaumont P (2013) A practical introduction to hardware/software codesign, 2nd edn. Springer Science+Business media, New York Shrivastava A, Kumar M (2000) Optimal hardware/software partitioning for concurrent specification using dynamic programming.
Bhuvaneswari and M. Jagadeeswari Initial Solution b 3 Nets Cut After swapping module 1 and 3 NETI 1 1 Nets Cut NET1 2 3 NET2 4 5 3 2 1 4 5 NET4 NET2 NET3 NET4 NET3 BLOCK(1) BLOCK(2) BLOCK(1) BLOCK(2) Fig. 1 Illustration of circuit bipartition elements into “k” blocks by enumerating all possible permutations in which “n” circuit components can be divided into “k” equal blocks of size p ¼ n/k. The total number of unique ways of partitioning the graph is given in Eq. 1. The equation becomes more complex when the number of nodes n is large and the bipartitioning problem (k ¼ 2) leads to nonpolynomial time (Mazumder and Rudnick 1999).